function_name
stringlengths 1
80
| function
stringlengths 14
10.6k
| comment
stringlengths 12
8.02k
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stringlengths 6
6.55k
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|---|---|---|---|
Chip_ADC_SetIntBits
|
void Chip_ADC_SetIntBits(LPC_ADC_T *pADC, uint32_t intMask)
{
uint32_t temp;
/* Read and write values may not be the same, write 0 to
undefined bits */
temp = pADC->INTEN & 0x001FFFE7;
pADC->INTEN = temp | intMask;
}
|
/* Set ADC interrupt bits (safe) */
|
Set ADC interrupt bits (safe)
|
Chip_ADC_ClearIntBits
|
void Chip_ADC_ClearIntBits(LPC_ADC_T *pADC, uint32_t intMask)
{
uint32_t temp;
/* Read and write values may not be the same, write 0 to
undefined bits */
temp = pADC->INTEN & 0x001FFFE7;
pADC->INTEN = temp & ~intMask;
}
|
/* Clear ADC interrupt bits (safe) */
|
Clear ADC interrupt bits (safe)
|
Chip_ADC_SetTHRSELBits
|
void Chip_ADC_SetTHRSELBits(LPC_ADC_T *pADC, uint32_t mask)
{
uint32_t temp;
/* Read and write values may not be the same, write 0 to
undefined bits */
temp = pADC->CHAN_THRSEL & 0x000001FE;
pADC->CHAN_THRSEL = temp | mask;
}
|
/* Set ADC threshold selection bits (safe) */
|
Set ADC threshold selection bits (safe)
|
Chip_ADC_ClearTHRSELBits
|
void Chip_ADC_ClearTHRSELBits(LPC_ADC_T *pADC, uint32_t mask)
{
uint32_t temp;
/* Read and write values may not be the same, write 0 to
undefined bits */
temp = pADC->CHAN_THRSEL & 0x000001FE;
pADC->CHAN_THRSEL = temp & ~mask;
}
|
/* Clear ADC threshold selection bits (safe) */
|
Clear ADC threshold selection bits (safe)
|
Chip_ADC_Init
|
void Chip_ADC_Init(LPC_ADC_T *pADC, uint32_t flags)
{
/* Power up ADC and enable ADC base clock */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_ADC_PD);
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC);
/* FIXME - LPC1125 UM describes ADC reset, but no ADC reset bit in SYSCTL.
It will be easier to init if ADC reset is there. */
#if 0
/* Reset ADC */
Chip_SYSCTL_PeriphReset(RESET_ADC0);
#else
/* Disable ADC interrupts */
pADC->INTEN = 0;
#endif
/* Set ADC control options */
pADC->CTRL = flags;
}
|
/* Initialize the ADC peripheral */
|
Initialize the ADC peripheral
|
Chip_ADC_SetClockRate
|
void Chip_ADC_SetClockRate(LPC_ADC_T *pADC, uint32_t rate)
{
Chip_ADC_SetDivider(pADC, (Chip_Clock_GetSystemClockRate() / rate) - 1);
}
|
/* Set ADC clock rate */
|
Set ADC clock rate
|
Chip_ADC_SetSequencerBits
|
void Chip_ADC_SetSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits)
{
uint32_t temp;
/* Read sequencer register and mask off bits 20..25 */
temp = pADC->SEQ_CTRL[seqIndex] & ~(0x3F << 20);
/* OR in passed bits */
pADC->SEQ_CTRL[seqIndex] = temp | bits;
}
|
/* Helper function for safely setting ADC sequencer register bits */
|
Helper function for safely setting ADC sequencer register bits
|
Chip_ADC_ClearSequencerBits
|
void Chip_ADC_ClearSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits)
{
uint32_t temp;
/* Read sequencer register and mask off bits 20..25 */
temp = pADC->SEQ_CTRL[seqIndex] & ~(0x3F << 20);
/* OR in passed bits */
pADC->SEQ_CTRL[seqIndex] = temp & ~bits;
}
|
/* Helper function for safely clearing ADC sequencer register bits */
|
Helper function for safely clearing ADC sequencer register bits
|
Chip_ADC_EnableInt
|
void Chip_ADC_EnableInt(LPC_ADC_T *pADC, uint32_t intMask)
{
Chip_ADC_SetIntBits(pADC, intMask);
}
|
/* Enable interrupts in ADC (sequencers A/B and overrun) */
|
Enable interrupts in ADC (sequencers A/B and overrun)
|
Chip_ADC_DisableInt
|
void Chip_ADC_DisableInt(LPC_ADC_T *pADC, uint32_t intMask)
{
Chip_ADC_ClearIntBits(pADC, intMask);
}
|
/* Disable interrupts in ADC (sequencers A/B and overrun) */
|
Disable interrupts in ADC (sequencers A/B and overrun)
|
Chip_ADC_SetThresholdInt
|
void Chip_ADC_SetThresholdInt(LPC_ADC_T *pADC, uint8_t ch, ADC_INTEN_THCMP_T thInt)
{
int shiftIndex = 3 + (ch * 2);
/* Clear current bits first */
Chip_ADC_ClearIntBits(pADC, (ADC_INTEN_CMP_MASK << shiftIndex));
/* Set new threshold interrupt type */
Chip_ADC_SetIntBits(pADC, ((uint32_t) thInt << shiftIndex));
}
|
/* Enable a threshold event interrupt in ADC */
|
Enable a threshold event interrupt in ADC
|
Chip_ADC_SelectTH0Channels
|
void Chip_ADC_SelectTH0Channels(LPC_ADC_T *pADC, uint32_t channels)
{
Chip_ADC_ClearTHRSELBits(pADC, channels);
}
|
/* Select threshold 0 values for comparison for selected channels */
|
Select threshold 0 values for comparison for selected channels
|
Chip_ADC_SelectTH1Channels
|
void Chip_ADC_SelectTH1Channels(LPC_ADC_T *pADC, uint32_t channels)
{
Chip_ADC_SetTHRSELBits(pADC, channels);
}
|
/* Select threshold 1 value for comparison for selected channels */
|
Select threshold 1 value for comparison for selected channels
|
Chip_GPIO_WriteDirBit
|
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
{
if (setting) {
pGPIO->DIR[port] |= 1UL << bit;
}
else {
pGPIO->DIR[port] &= ~(1UL << bit);
}
}
|
/* Set a GPIO direction */
|
Set a GPIO direction
|
Chip_GPIO_SetDir
|
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)
{
if (out) {
pGPIO->DIR[portNum] |= bitValue;
}
else {
pGPIO->DIR[portNum] &= ~bitValue;
}
}
|
/* Set Direction for a GPIO port */
|
Set Direction for a GPIO port
|
Chip_GPIO_SetPinDIR
|
void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
{
if (output) {
Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
}
else {
Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
}
}
|
/* Set GPIO direction for a single GPIO pin */
|
Set GPIO direction for a single GPIO pin
|
Chip_GPIO_SetPortDIR
|
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask, bool outSet)
{
if (outSet) {
Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
}
}
|
/* Set GPIO direction for a all selected GPIO pins to an input or output */
|
Set GPIO direction for a all selected GPIO pins to an input or output
|
Chip_SystemInit
|
void Chip_SystemInit(void)
{
/* IRC should be powered up */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
/* Enable IOCON clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
}
|
/* Set up and initialize hardware prior to call to main */
|
Set up and initialize hardware prior to call to main
|
getFullConvClk
|
STATIC INLINE uint8_t getFullConvClk(void)
{
return 11;
}
|
/* Get the number of clock for a full conversion */
|
Get the number of clock for a full conversion
|
getClkDiv
|
STATIC uint8_t getClkDiv(LPC_ADC_T *pADC, bool burstMode, uint32_t adcRate, uint8_t clks)
{
uint32_t adcBlockFreq;
uint32_t fullAdcRate;
uint8_t div;
/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
A/D converter, which should be less than or equal to 4.5MHz.
A fully conversion requires (bits_accuracy+1) of these clocks.
ADC Clock = PCLK_ADC0 / (CLKDIV + 1);
ADC rate = ADC clock / (the number of clocks required for each conversion);
*/
adcBlockFreq = Chip_Clock_GetSystemClockRate();
if (burstMode) {
fullAdcRate = adcRate * clks;
}
else {
fullAdcRate = adcRate * getFullConvClk();
}
/* Get the round value by fomular: (2*A + B)/(2*B) */
div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1;
return div;
}
|
/* Get divider value */
|
Get divider value
|
setStartMode
|
void setStartMode(LPC_ADC_T *pADC, uint8_t start_mode)
{
uint32_t temp;
temp = pADC->CR & (~ADC_CR_START_MASK);
pADC->CR = temp | (ADC_CR_START_MODE_SEL((uint32_t) start_mode));
}
|
/* Set start mode for ADC */
|
Set start mode for ADC
|
readAdcVal
|
Status readAdcVal(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
{
uint32_t temp;
temp = pADC->DR[channel];
if (!ADC_DR_DONE(temp)) {
return ERROR;
}
/* if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST)) */
/* return ERROR; */
*data = (uint16_t) ADC_DR_RESULT(temp);
return SUCCESS;
}
|
/* Get the ADC value */
|
Get the ADC value
|
Chip_ADC_Init
|
void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup)
{
uint8_t div;
uint32_t cr = 0;
uint32_t clk;
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_ADC_PD);
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC);
pADC->INTEN = 0; /* Disable all interrupts */
cr |= ADC_CR_PDN;
ADCSetup->adcRate = ADC_MAX_SAMPLE_RATE;
ADCSetup->bitsAccuracy = ADC_10BITS;
clk = 11;
ADCSetup->burstMode = false;
div = getClkDiv(pADC, false, ADCSetup->adcRate, clk);
cr |= ADC_CR_CLKDIV(div);
cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
pADC->CR = cr;
}
|
/* Initialize the ADC peripheral and the ADC setup structure to default value */
|
Initialize the ADC peripheral and the ADC setup structure to default value
|
Chip_ADC_ReadValue
|
Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
{
return readAdcVal(pADC, channel, data);
}
|
/* Get the ADC value */
|
Get the ADC value
|
Chip_ADC_ReadStatus
|
FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType)
{
switch (StatusType) {
case ADC_DR_DONE_STAT:
return (pADC->STAT & (1UL << channel)) ? SET : RESET;
case ADC_DR_OVERRUN_STAT:
channel += 8;
return (pADC->STAT & (1UL << channel)) ? SET : RESET;
case ADC_DR_ADINT_STAT:
return pADC->STAT >> 16 ? SET : RESET;
default:
break;
}
return RESET;
}
|
/* Get ADC Channel status from ADC data register */
|
Get ADC Channel status from ADC data register
|
Chip_ADC_Int_SetChannelCmd
|
void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState)
{
if (NewState == ENABLE) {
pADC->INTEN |= (1UL << channel);
}
else {
pADC->INTEN &= (~(1UL << channel));
}
}
|
/* Enable/Disable interrupt for ADC channel */
|
Enable/Disable interrupt for ADC channel
|
Chip_ADC_SetStartMode
|
void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption)
{
if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
if (EdgeOption) {
pADC->CR |= ADC_CR_EDGE;
}
else {
pADC->CR &= ~ADC_CR_EDGE;
}
}
setStartMode(pADC, (uint8_t) mode);
}
|
/* Select the mode starting the AD conversion */
|
Select the mode starting the AD conversion
|
Chip_ADC_SetSampleRate
|
void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate)
{
uint8_t div;
uint32_t cr;
cr = pADC->CR & (~ADC_SAMPLE_RATE_CONFIG_MASK);
ADCSetup->adcRate = rate;
div = getClkDiv(pADC, ADCSetup->burstMode, rate, (11 - ADCSetup->bitsAccuracy));
cr |= ADC_CR_CLKDIV(div);
cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
pADC->CR = cr;
}
|
/* Set the ADC Sample rate */
|
Set the ADC Sample rate
|
Chip_ADC_SetResolution
|
void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution)
{
ADCSetup->bitsAccuracy = resolution;
Chip_ADC_SetSampleRate(pADC, ADCSetup, ADCSetup->adcRate);
}
|
/* Set the ADC accuracy bits */
|
Set the ADC accuracy bits
|
Chip_ADC_EnableChannel
|
void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState)
{
if (NewState == ENABLE) {
pADC->CR |= ADC_CR_CH_SEL(channel);
}
else {
pADC->CR &= ~ADC_CR_START_MASK;
pADC->CR &= ~ADC_CR_CH_SEL(channel);
}
}
|
/* Enable or disable the ADC channel on ADC peripheral */
|
Enable or disable the ADC channel on ADC peripheral
|
Chip_ADC_SetBurstCmd
|
void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState)
{
setStartMode(pADC, ADC_NO_START);
if (NewState == DISABLE) {
pADC->CR &= ~ADC_CR_BURST;
}
else {
pADC->CR |= ADC_CR_BURST;
}
}
|
/* Enable burst mode */
|
Enable burst mode
|
Chip_ADC_ReadByte
|
Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data)
{
uint16_t temp = 0;
Status rt;
rt = readAdcVal(pADC, channel, &temp);
*data = (uint8_t) temp;
return rt;
}
|
/* Read the ADC value and convert it to 8bits value */
|
Read the ADC value and convert it to 8bits value
|
Chip_PMU_SleepState
|
void Chip_PMU_SleepState(LPC_PMU_T *pPMU)
{
pPMU->PCON = PMU_PCON_PM_SLEEP;
/* Enter sleep mode */
__WFI();
}
|
/* Enter MCU Sleep mode */
|
Enter MCU Sleep mode
|
Chip_PMU_DeepSleepState
|
void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU)
{
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
pPMU->PCON = PMU_PCON_PM_DEEPSLEEP;
/* Enter sleep mode */
__WFI();
}
|
/* Enter MCU Deep Sleep mode */
|
Enter MCU Deep Sleep mode
|
Chip_PMU_PowerDownState
|
void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU)
{
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
pPMU->PCON = PMU_PCON_PM_POWERDOWN;
/* Enter sleep mode */
__WFI();
}
|
/* Enter MCU Power down mode */
|
Enter MCU Power down mode
|
Chip_PMU_DeepPowerDownState
|
void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU)
{
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
pPMU->PCON = PMU_PCON_PM_DEEPPOWERDOWN;
/* Enter sleep mode */
__WFI();
}
|
/* Enter MCU Deep Power down mode */
|
Enter MCU Deep Power down mode
|
Chip_PMU_Sleep
|
void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode)
{
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
if (SleepMode == PMU_MCU_DEEP_SLEEP) {
Chip_PMU_DeepSleepState(pPMU);
}
else if (SleepMode == PMU_MCU_POWER_DOWN) {
Chip_PMU_PowerDownState(pPMU);
}
else if (SleepMode == PMU_MCU_DEEP_PWRDOWN) {
Chip_PMU_DeepPowerDownState(pPMU);
}
else {
/* PMU_MCU_SLEEP */
Chip_PMU_SleepState(pPMU);
}
#elif defined(CHIP_LPC11CXX)
if (SleepMode == PMU_MCU_DEEP_PWRDOWN) {
Chip_PMU_DeepPowerDownState(pPMU);
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */
}
|
/* Put some of the peripheral in sleep mode */
|
Put some of the peripheral in sleep mode
|
Chip_UART_Init
|
void Chip_UART_Init(LPC_USART_T *pUART)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_UART0);
Chip_Clock_SetUARTClockDiv(1);
/* Enable FIFOs by default, reset them */
Chip_UART_SetupFIFOS(pUART, (UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS));
/* Default 8N1, with DLAB disabled */
Chip_UART_ConfigData(pUART, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS));
/* Disable fractional divider */
pUART->FDR = 0x10;
}
|
/* Initializes the pUART peripheral */
|
Initializes the pUART peripheral
|
Chip_UART_DeInit
|
void Chip_UART_DeInit(LPC_USART_T *pUART)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_UART0);
}
|
/* De-initializes the pUART peripheral */
|
De-initializes the pUART peripheral
|
Chip_UART_Send
|
int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes)
{
int sent = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((sent < numBytes) &&
((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0)) {
Chip_UART_SendByte(pUART, *p8);
p8++;
sent++;
}
return sent;
}
|
/* Transmit a byte array through the UART peripheral (non-blocking) */
|
Transmit a byte array through the UART peripheral (non-blocking)
|
Chip_UART_Read
|
int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes)
{
int readBytes = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((readBytes < numBytes) &&
((Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) != 0)) {
*p8 = Chip_UART_ReadByte(pUART);
p8++;
readBytes++;
}
return readBytes;
}
|
/* Read data through the UART peripheral (non-blocking) */
|
Read data through the UART peripheral (non-blocking)
|
Chip_UART_SetBaud
|
uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate)
{
uint32_t div, divh, divl, clkin;
/* Determine UART clock in rate without FDR */
clkin = Chip_Clock_GetMainClockRate();
div = clkin / (baudrate * 16);
/* High and low halves of the divider */
divh = div / 256;
divl = div - (divh * 256);
Chip_UART_EnableDivisorAccess(pUART);
Chip_UART_SetDivisorLatches(pUART, divl, divh);
Chip_UART_DisableDivisorAccess(pUART);
/* Fractional FDR alreadt setup for 1 in UART init */
return clkin / div;
}
|
/* Determines and sets best dividers to get a target bit rate */
|
Determines and sets best dividers to get a target bit rate
|
Chip_UART_RXIntHandlerRB
|
void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
/* New data will be ignored if data not popped in time */
while (Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) {
uint8_t ch = Chip_UART_ReadByte(pUART);
RingBuffer_Insert(pRB, &ch);
}
}
|
/* UART receive-only interrupt handler for ring buffers */
|
UART receive-only interrupt handler for ring buffers
|
Chip_UART_TXIntHandlerRB
|
void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
uint8_t ch;
/* Fill FIFO until full or until TX ring buffer is empty */
while ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0 &&
RingBuffer_Pop(pRB, &ch)) {
Chip_UART_SendByte(pUART, ch);
}
}
|
/* UART transmit-only interrupt handler for ring buffers */
|
UART transmit-only interrupt handler for ring buffers
|
Chip_UART_SendRB
|
uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes)
{
uint32_t ret;
uint8_t *p8 = (uint8_t *) data;
/* Don't let UART transmit ring buffer change in the UART IRQ handler */
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
/* Move as much data as possible into transmit ring buffer */
ret = RingBuffer_InsertMult(pRB, p8, bytes);
Chip_UART_TXIntHandlerRB(pUART, pRB);
/* Add additional data to transmit ring buffer if possible */
ret += RingBuffer_InsertMult(pRB, (p8 + ret), (bytes - ret));
/* Enable UART transmit interrupt */
Chip_UART_IntEnable(pUART, UART_IER_THREINT);
return ret;
}
|
/* Populate a transmit ring buffer and start UART transmit */
|
Populate a transmit ring buffer and start UART transmit
|
Chip_UART_IRQRBHandler
|
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB)
{
/* Handle transmit interrupt if enabled */
if (pUART->IER & UART_IER_THREINT) {
Chip_UART_TXIntHandlerRB(pUART, pTXRB);
/* Disable transmit interrupt if the ring buffer is empty */
if (RingBuffer_IsEmpty(pTXRB)) {
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
}
}
/* Handle receive interrupt */
Chip_UART_RXIntHandlerRB(pUART, pRXRB);
}
|
/* UART receive/transmit interrupt handler for ring buffers */
|
UART receive/transmit interrupt handler for ring buffers
|
Chip_GPIO_WriteDirBit
|
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
{
if (setting) {
pGPIO[port].DIR |= 1UL << bit;
}
else {
pGPIO[port].DIR &= ~(1UL << bit);
}
}
|
/* Set GPIO direction */
|
Set GPIO direction
|
Chip_GPIO_SetDir
|
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit, uint8_t out)
{
if (out) {
pGPIO[port].DIR |= bit;
}
else {
pGPIO[port].DIR &= ~bit;
}
}
|
/* Set Direction for a GPIO port */
|
Set Direction for a GPIO port
|
Chip_GPIO_SetPortDIR
|
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet)
{
if (outSet) {
Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
}
}
|
/* Set GPIO direction for a all selected GPIO pins to an input or output */
|
Set GPIO direction for a all selected GPIO pins to an input or output
|
Chip_GPIO_SetupPinInt
|
void Chip_GPIO_SetupPinInt(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, GPIO_INT_MODE_T mode)
{
uint32_t pinMask = (1 << pin);
/* Edge mode selected? */
if ((uint32_t) mode & 0x2) {
Chip_GPIO_SetPinModeEdge(pGPIO, port, pinMask);
/* Interrupt on both edges selected? */
if ((uint32_t) mode & 0x4) {
Chip_GPIO_SetEdgeModeBoth(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetEdgeModeSingle(pGPIO, port, pinMask);
}
}
else {
/* Level mode */
Chip_GPIO_SetPinModeLevel(pGPIO, port, pinMask);
}
/* Level selections will not alter 'dual edge' mode */
if ((uint32_t) mode & 0x1) {
/* High edge or level mode selected */
Chip_GPIO_SetModeHigh(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetModeLow(pGPIO, port, pinMask);
}
}
|
/* Composite function for setting up a full interrupt configuration for a single pin */
|
Composite function for setting up a full interrupt configuration for a single pin
|
Chip_I2CM_Init
|
void Chip_I2CM_Init(LPC_I2C_T *pI2C)
{
/* Enable I2C clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_I2C);
/* Peripheral reset control to I2C */
Chip_SYSCTL_PeriphReset(RESET_I2C0);
}
|
/* Initializes the LPC_I2C peripheral with specified parameter */
|
Initializes the LPC_I2C peripheral with specified parameter
|
Chip_I2CM_DeInit
|
void Chip_I2CM_DeInit(LPC_I2C_T *pI2C)
{
/* Disable I2C clock */
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_I2C);
}
|
/* De-initializes the I2C peripheral registers to their default reset values */
|
De-initializes the I2C peripheral registers to their default reset values
|
Chip_I2CM_SetBusSpeed
|
void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed)
{
uint32_t clockDiv = (Chip_Clock_GetMainClockRate() / busSpeed);
Chip_I2CM_SetDutyCycle(pI2C, (clockDiv >> 1), (clockDiv - (clockDiv >> 1)));
}
|
/* Set up bus speed for LPC_I2C interface */
|
Set up bus speed for LPC_I2C interface
|
Chip_I2CM_Xfer
|
void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
/* set the transfer status as busy */
xfer->status = I2CM_STATUS_BUSY;
/* Clear controller state. */
Chip_I2CM_ResetControl(pI2C);
/* Enter to Master Transmitter mode */
Chip_I2CM_SendStart(pI2C);
}
|
/* Transmit and Receive data in master mode */
|
Transmit and Receive data in master mode
|
Chip_I2CM_XferBlocking
|
uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
uint32_t ret = 0;
/* start transfer */
Chip_I2CM_Xfer(pI2C, xfer);
while (ret == 0) {
/* wait for status change interrupt */
while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
/* call state change handler */
ret = Chip_I2CM_XferHandler(pI2C, xfer);
}
return ret;
}
|
/* Transmit and Receive data in master mode */
|
Transmit and Receive data in master mode
|
Chip_I2CM_Write
|
uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len)
{
uint32_t txLen = 0, err = 0;
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
/* generate START condition */
Chip_I2CM_SendStart(pI2C);
while ((txLen < len) && (err == 0)) {
/* wait for status change interrupt */
while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
/* check status and send data */
switch (Chip_I2CM_GetCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
case 0x18: /* SLA+W sent and ACK received */
case 0x28: /* DATA sent and ACK received */
Chip_I2CM_WriteByte(pI2C, buff[txLen++]);
break;
case 0x38: /* Arbitration lost */
break;
default: /* we shouldn't be in any other state */
err = 1;
break;
}
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
}
return txLen;
}
|
/* Master tx only */
|
Master tx only
|
Chip_I2CM_Read
|
uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len)
{
uint32_t rxLen = 0, err = 0;
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
/* generate START condition and auto-ack data received */
pI2C->CONSET = I2C_CON_AA | I2C_CON_STA;
while ((rxLen < len) && (err == 0)) {
/* wait for status change interrupt */
while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
/* check status and send data */
switch (Chip_I2CM_GetCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
case 0x40: /* SLA+R sent and ACK received */
case 0x50: /* Data Received and ACK sent */
buff[rxLen++] = Chip_I2CM_ReadByte(pI2C);
break;
case 0x38: /* Arbitration lost */
break;
default: /* we shouldn't be in any other state */
err = 1;
break;
}
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
}
return rxLen;
}
|
/* Sequential master read */
|
Sequential master read
|
SSP_Write1BFifo
|
STATIC void SSP_Write1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
if (xf_setup->tx_data) {
Chip_SSP_SendFrame(pSSP, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
}
else {
Chip_SSP_SendFrame(pSSP, 0xFF);
}
xf_setup->tx_cnt++;
}
|
/** SSP macro: write 1 bytes to FIFO buffer */
|
SSP macro: write 1 bytes to FIFO buffer
|
SSP_Read2BFifo
|
STATIC void SSP_Read2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
uint16_t rDat;
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
(xf_setup->rx_cnt < xf_setup->length)) {
rDat = Chip_SSP_ReceiveFrame(pSSP);
if (xf_setup->rx_data) {
*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
}
xf_setup->rx_cnt += 2;
}
}
|
/** SSP macro: read 1 bytes from FIFO buffer */
|
SSP macro: read 1 bytes from FIFO buffer
|
SSP_Read1BFifo
|
STATIC void SSP_Read1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
uint16_t rDat;
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
(xf_setup->rx_cnt < xf_setup->length)) {
rDat = Chip_SSP_ReceiveFrame(pSSP);
if (xf_setup->rx_data) {
*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
}
xf_setup->rx_cnt++;
}
}
|
/** SSP macro: read 2 bytes from FIFO buffer */
|
SSP macro: read 2 bytes from FIFO buffer
|
Chip_SSP_GetClockIndex
|
STATIC CHIP_SYSCTL_CLOCK_T Chip_SSP_GetClockIndex(LPC_SSP_T *pSSP)
{
CHIP_SYSCTL_CLOCK_T clkSSP;
if (pSSP == LPC_SSP0) {
clkSSP = SYSCTL_CLOCK_SSP0;
}
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
else {
clkSSP = SYSCTL_CLOCK_SSP1;
}
#endif
return clkSSP;
}
|
/* Returns clock for the peripheral block */
|
Returns clock for the peripheral block
|
Chip_SSP_GetResetIndex
|
STATIC CHIP_SYSCTL_PERIPH_RESET_T Chip_SSP_GetResetIndex(LPC_SSP_T *pSSP)
{
CHIP_SYSCTL_PERIPH_RESET_T resetSSP;
if (pSSP == LPC_SSP0) {
resetSSP = RESET_SSP0;
}
else {
resetSSP = RESET_SSP1;
}
return resetSSP;
}
|
/* Returns reset ID for the peripheral block */
|
Returns reset ID for the peripheral block
|
Chip_SSP_SetSSPClkDivider
|
STATIC void Chip_SSP_SetSSPClkDivider(LPC_SSP_T *pSSP, uint32_t div)
{
if (pSSP == LPC_SSP0) {
Chip_Clock_SetSSP0ClockDiv(div);
}
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
else {
Chip_Clock_SetSSP1ClockDiv(div);
}
#endif
}
|
/* Returns reset ID for the peripheral block */
|
Returns reset ID for the peripheral block
|
Chip_SSP_GetPCLKkRate
|
STATIC uint32_t Chip_SSP_GetPCLKkRate(LPC_SSP_T *pSSP)
{
uint32_t sspCLK = Chip_Clock_GetMainClockRate();
if (pSSP == LPC_SSP0) {
sspCLK /= Chip_Clock_GetSSP0ClockDiv();
}
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
else {
sspCLK /= Chip_Clock_GetSSP1ClockDiv();
}
#endif
return sspCLK;
}
|
/* Returns SSP peripheral clock for the peripheral block */
|
Returns SSP peripheral clock for the peripheral block
|
Chip_SSP_SetClockRate
|
void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
{
uint32_t temp;
temp = pSSP->CR0 & (~(SSP_CR0_SCR(0xFF)));
pSSP->CR0 = temp | (SSP_CR0_SCR(clk_rate));
pSSP->CPSR = prescale;
}
|
/*Set up output clocks per bit for SSP bus*/
|
Set up output clocks per bit for SSP bus
|
Chip_SSP_Int_FlushData
|
void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP)
{
if (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {}
}
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
}
|
/* Clean all data in RX FIFO of SSP */
|
Clean all data in RX FIFO of SSP
|
Chip_SSP_SetMaster
|
void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master)
{
if (master) {
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
}
else {
Chip_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE);
}
}
|
/* Set the SSP operating modes, master or slave */
|
Set the SSP operating modes, master or slave
|
Chip_SSP_SetBitRate
|
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate)
{
uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
ssp_clk = Chip_SSP_GetPCLKkRate(pSSP);
cr0_div = 0;
cmp_clk = 0xFFFFFFFF;
prescale = 2;
while (cmp_clk > bitRate) {
cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
if (cmp_clk > bitRate) {
cr0_div++;
if (cr0_div > 0xFF) {
cr0_div = 0;
prescale += 2;
}
}
}
Chip_SSP_SetClockRate(pSSP, cr0_div, prescale);
}
|
/* Set the clock frequency for SSP interface */
|
Set the clock frequency for SSP interface
|
Chip_SSP_Init
|
void Chip_SSP_Init(LPC_SSP_T *pSSP)
{
Chip_Clock_EnablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
Chip_SSP_SetSSPClkDivider(pSSP, 1);
Chip_SYSCTL_PeriphReset(Chip_SSP_GetResetIndex(pSSP));
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
Chip_SSP_SetFormat(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
Chip_SSP_SetBitRate(pSSP, 100000);
}
|
/* Initialize the SSP */
|
Initialize the SSP
|
Chip_SSP_DeInit
|
void Chip_SSP_DeInit(LPC_SSP_T *pSSP)
{
Chip_SSP_Disable(pSSP);
Chip_Clock_DisablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
Chip_SSP_SetSSPClkDivider(pSSP, 0);
}
|
/* De-initializes the SSP peripheral */
|
De-initializes the SSP peripheral
|
getClkRate
|
STATIC INLINE uint32_t getClkRate(I2C_ID_T id)
{
return Chip_Clock_GetMainClockRate();
}
|
/* Get the ADC Clock Rate */
|
Get the ADC Clock Rate
|
startMasterXfer
|
STATIC INLINE void startMasterXfer(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
/* Enter to Master Transmitter mode */
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
}
|
/* Enable I2C and start master transfer */
|
Enable I2C and start master transfer
|
startSlaverXfer
|
STATIC INLINE void startSlaverXfer(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
/* Enter to Master Transmitter mode */
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;
}
|
/* Enable I2C and enable slave transfers */
|
Enable I2C and enable slave transfers
|
isI2CBusFree
|
STATIC INLINE int isI2CBusFree(LPC_I2C_T *pI2C)
{
return !(pI2C->CONSET & I2C_CON_STO);
}
|
/* Check if I2C bus is free */
|
Check if I2C bus is free
|
getCurState
|
STATIC INLINE int getCurState(LPC_I2C_T *pI2C)
{
return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);
}
|
/* Get current state of the I2C peripheral */
|
Get current state of the I2C peripheral
|
isMasterState
|
STATIC INLINE int isMasterState(LPC_I2C_T *pI2C)
{
return getCurState(pI2C) < 0x60;
}
|
/* Check if the active state belongs to master mode*/
|
Check if the active state belongs to master mode
|
setSlaveAddr
|
STATIC void setSlaveAddr(LPC_I2C_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)
{
uint32_t index = (uint32_t) sid - 1;
pI2C->MASK[index] = mask;
if (sid == I2C_SLAVE_0) {
pI2C->ADR0 = addr;
}
else {
volatile uint32_t *abase = &pI2C->ADR1;
abase[index - 1] = addr;
}
}
|
/* Set OWN slave address for specific slave ID */
|
Set OWN slave address for specific slave ID
|
isSlaveAddrMatching
|
STATIC int isSlaveAddrMatching(uint8_t addr1, uint8_t addr2, uint8_t mask)
{
mask |= 1;
return (addr1 & ~mask) == (addr2 & ~mask);
}
|
/* Match the slave address */
|
Match the slave address
|
lookupSlaveIndex
|
STATIC I2C_SLAVE_ID lookupSlaveIndex(LPC_I2C_T *pI2C, uint8_t slaveAddr)
{
if (!(slaveAddr >> 1)) {
return I2C_SLAVE_GENERAL; /* General call address */
}
if (isSlaveAddrMatching(pI2C->ADR0, slaveAddr, pI2C->MASK[0])) {
return I2C_SLAVE_0;
}
if (isSlaveAddrMatching(pI2C->ADR1, slaveAddr, pI2C->MASK[1])) {
return I2C_SLAVE_1;
}
if (isSlaveAddrMatching(pI2C->ADR2, slaveAddr, pI2C->MASK[2])) {
return I2C_SLAVE_2;
}
if (isSlaveAddrMatching(pI2C->ADR3, slaveAddr, pI2C->MASK[3])) {
return I2C_SLAVE_3;
}
/* If everything is fine the code should never come here */
return I2C_SLAVE_GENERAL;
}
|
/* Get the index of the active slave */
|
Get the index of the active slave
|
getSlaveIndex
|
I2C_SLAVE_ID getSlaveIndex(LPC_I2C_T *pI2C)
{
switch (getCurState(pI2C)) {
case 0x60:
case 0x68:
case 0x70:
case 0x78:
case 0xA8:
case 0xB0:
return lookupSlaveIndex(pI2C, pI2C->DAT);
}
/* If everything is fine code should never come here */
return I2C_SLAVE_GENERAL;
}
|
/* Find the slave address of SLA+W or SLA+R */
|
Find the slave address of SLA+W or SLA+R
|
Chip_I2C_EventHandler
|
void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event)
{
struct i2c_interface *iic = &i2c[id];
volatile I2C_STATUS_T *stat;
/* Only WAIT event needs to be handled */
if (event != I2C_EVENT_WAIT) {
return;
}
stat = &iic->mXfer->status;
/* Wait for the status to change */
while (*stat == I2C_STATUS_BUSY) {}
}
|
/* Chip event handler interrupt based */
|
Chip event handler interrupt based
|
Chip_I2C_EventHandlerPolling
|
void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event)
{
struct i2c_interface *iic = &i2c[id];
volatile I2C_STATUS_T *stat;
/* Only WAIT event needs to be handled */
if (event != I2C_EVENT_WAIT) {
return;
}
stat = &iic->mXfer->status;
/* Call the state change handler till xfer is done */
while (*stat == I2C_STATUS_BUSY) {
if (Chip_I2C_IsStateChanged(id)) {
Chip_I2C_MasterStateHandler(id);
}
}
}
|
/* Chip polling event handler */
|
Chip polling event handler
|
Chip_I2C_Init
|
void Chip_I2C_Init(I2C_ID_T id)
{
enableClk(id);
/* Set I2C operation to default */
LPC_I2Cx(id)->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);
}
|
/* Initializes the LPC_I2C peripheral with specified parameter */
|
Initializes the LPC_I2C peripheral with specified parameter
|
Chip_I2C_DeInit
|
void Chip_I2C_DeInit(I2C_ID_T id)
{
/* Disable I2C control */
LPC_I2Cx(id)->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
disableClk(id);
}
|
/* De-initializes the I2C peripheral registers to their default reset values */
|
De-initializes the I2C peripheral registers to their default reset values
|
Chip_I2C_SetClockRate
|
void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate)
{
uint32_t SCLValue;
SCLValue = (getClkRate(id) / clockrate);
LPC_I2Cx(id)->SCLH = (uint32_t) (SCLValue >> 1);
LPC_I2Cx(id)->SCLL = (uint32_t) (SCLValue - LPC_I2Cx(id)->SCLH);
}
|
/* Set up clock rate for LPC_I2C peripheral */
|
Set up clock rate for LPC_I2C peripheral
|
Chip_I2C_GetClockRate
|
uint32_t Chip_I2C_GetClockRate(I2C_ID_T id)
{
return getClkRate(id) / (LPC_I2Cx(id)->SCLH + LPC_I2Cx(id)->SCLL);
}
|
/* Get current clock rate for LPC_I2C peripheral */
|
Get current clock rate for LPC_I2C peripheral
|
Chip_I2C_SetMasterEventHandler
|
int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event)
{
struct i2c_interface *iic = &i2c[id];
if (!iic->mXfer) {
iic->mEvent = event;
}
return iic->mEvent == event;
}
|
/* Set the master event handler */
|
Set the master event handler
|
Chip_I2C_GetMasterEventHandler
|
I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id)
{
return i2c[id].mEvent;
}
|
/* Get the master event handler */
|
Get the master event handler
|
Chip_I2C_MasterTransfer
|
int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer)
{
struct i2c_interface *iic = &i2c[id];
iic->mEvent(id, I2C_EVENT_LOCK);
xfer->status = I2C_STATUS_BUSY;
iic->mXfer = xfer;
/* If slave xfer not in progress */
if (!iic->sXfer) {
startMasterXfer(iic->ip);
}
iic->mEvent(id, I2C_EVENT_WAIT);
iic->mXfer = 0;
/* Wait for stop condition to appear on bus */
while (!isI2CBusFree(iic->ip)) {}
/* Start slave if one is active */
if (SLAVE_ACTIVE(iic)) {
startSlaverXfer(iic->ip);
}
iic->mEvent(id, I2C_EVENT_UNLOCK);
return (int) xfer->status;
}
|
/* Transmit and Receive data in master mode */
|
Transmit and Receive data in master mode
|
Chip_I2C_MasterSend
|
int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.txBuff = buff;
xfer.txSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.txSz;
}
|
/* Master tx only */
|
Master tx only
|
Chip_I2C_MasterCmdRead
|
int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.txBuff = &cmd;
xfer.txSz = 1;
xfer.rxBuff = buff;
xfer.rxSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.rxSz;
}
|
/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode.
* This function is useful for communicating with the I2C slave registers
*/
|
Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode. This function is useful for communicating with the I2C slave registers
|
Chip_I2C_MasterRead
|
int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.rxBuff = buff;
xfer.rxSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.rxSz;
}
|
/* Sequential master read */
|
Sequential master read
|
Chip_I2C_IsMasterActive
|
int Chip_I2C_IsMasterActive(I2C_ID_T id)
{
return isMasterState(i2c[id].ip);
}
|
/* Check if master state is active */
|
Check if master state is active
|
Chip_I2C_MasterStateHandler
|
void Chip_I2C_MasterStateHandler(I2C_ID_T id)
{
if (!handleMasterXferState(i2c[id].ip, i2c[id].mXfer)) {
i2c[id].mEvent(id, I2C_EVENT_DONE);
}
}
|
/* State change handler for master transfer */
|
State change handler for master transfer
|
Chip_I2C_SlaveSetup
|
void Chip_I2C_SlaveSetup(I2C_ID_T id,
I2C_SLAVE_ID sid,
I2C_XFER_T *xfer,
I2C_EVENTHANDLER_T event,
uint8_t addrMask)
{
struct i2c_interface *iic = &i2c[id];
struct i2c_slave_interface *si2c = &i2c_slave[id][sid];
si2c->xfer = xfer;
si2c->event = event;
/* Set up the slave address */
if (sid != I2C_SLAVE_GENERAL) {
setSlaveAddr(iic->ip, sid, xfer->slaveAddr, addrMask);
}
if (!SLAVE_ACTIVE(iic) && !iic->mXfer) {
startSlaverXfer(iic->ip);
}
iic->flags |= 1 << (sid + 8);
}
|
/* Setup slave function */
|
Setup slave function
|
Chip_I2C_Disable
|
void Chip_I2C_Disable(I2C_ID_T id)
{
LPC_I2Cx(id)->CONCLR = I2C_I2CONCLR_I2ENC;
}
|
/* Disable I2C device */
|
Disable I2C device
|
Chip_I2C_IsStateChanged
|
int Chip_I2C_IsStateChanged(I2C_ID_T id)
{
return (LPC_I2Cx(id)->CONSET & I2C_CON_SI) != 0;
}
|
/* State change checking */
|
State change checking
|
Chip_IOCON_PinMuxSet
|
void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc)
{
if (port == 0) {
pIOCON->PIO0[pin] = modefunc;
}
else {
pIOCON->PIO1[pin] = modefunc;
}
}
|
/* Sets I/O Control pin mux */
|
Sets I/O Control pin mux
|
Chip_Clock_GetPLLFreq
|
STATIC uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
{
uint32_t msel = ((PLLReg & 0x1F) + 1);
return inputRate * msel;
}
|
/* Compute a PLL frequency */
|
Compute a PLL frequency
|
Chip_Clock_SetUSBPLLSource
|
void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
{
LPC_SYSCTL->USBPLLCLKSEL = (uint32_t) src;
LPC_SYSCTL->USBPLLCLKUEN = 0;
LPC_SYSCTL->USBPLLCLKUEN = 1;
}
|
/* Set USB PLL clock source */
|
Set USB PLL clock source
|
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